The three major categories of switch fabrics are: shared medium, shared memory and space division architectures. Most of the commercially available switch fabrics are small (with fewer than 32 input and output lines) built using shared memory or shared medium concept, both of which are inherently non-scaleable. Many, if not all, of the firms building switch fabrics are not currently concerned about the need to look for more scaleable architectures. Researchers have predicted that networks based on space division architecture are bound to become popular in the future, when larger switch fabrics will be required. However, most of these space division architectures reported in the literature are variations and enhancements of the banyan network, which is a multistage interconnection network (MIN) based on 2x2 switching elements. Results of research at Memorial have shown that banyan based systems require an excessive amount of buffering and are inefficient.
The balanced gamma (BG) network, developed by Venkatesan and his research collaborators, is a MIN based on 4x4 switching elements. The BG network has been shown to possess much superior packet loss rates under bursty traffic conditions, and consequently it requires much fewer buffers to obtain acceptable overall performance. The BG network has also been shown to possess fault tolerance, high reliability and good robustness. A simulation software to study the performance of different MIN architectures under various traffic conditions has been developed at Memorial. This software will be available for carrying out the proposed research. Following extensive simulation studies, the essential elements of the BG network are now being designed by a graduate student. However, a complete design of a large (say with 64 or 128 input / output lines) BG network and a thorough testing of the network will be required for convincing the switch fabric manufacturers of the superiority of the BG network over the other competing architectures. The test hardware presently available at the university may be adequate for the functional testing of a single switch block, but are certainly inadequate for testing a moderate size network at operating speed. The second part of the project would involve testing of the device(s) in an organization which has facilities to conduct such testing. Preliminary discussions to this end are already underway with TELIA, Sweden.
One of the principle implementation methodologies for the new standard will be digital hardware and Memorial is poised to contribute significantly to the study of the digital hardware implementations of the candidates for the new standard. Previous work in this area investigated the design of the programmable logic device implementation of a novel encryption algorithm. Recently completed work focussed on the digital hardware implementation of 2 encryption algorithms proposed for AES. Work is expected to continue in this direction for some time, as the practical implementation of proposed ciphers has yet to be fully explored.