Research area: 

 

Hardware Implementation and performance analysis of ciphers and  cryptographic algorithms related to Internet security.

 

Cryptographic ciphers and algorithms and be implemented either in software or in hardware. Software implementations have inherent limitations due to speed and security. The speed is restricted to the speed of computing platform and there are vulnerabilities for viruses and other complications due to system failures. On the other hand a hardware implementation is faster and it enhances the security by protecting against internal and external intruders and also provides physical security. For hardware implementations of this nature, re-configurable technology such as the Field Programmable Gate Array (FPGA) offers many advantages over semi-custom Application Specific Integrated Circuits (ASICs). FPGAs assure a short time to the market, high flexibility including capability for frequent modifications of hardware, low development cost and low cost of the final product. It has the potential for fast, low cost reprogramming and experimental testing of a large number of various architectures and revised versions of the same architecture.

 

 

Hardware implementation Tools: Xilinx Alliance, Xilinx Foundation, Synopsys, Cadence, FPGA Express, ModelSim, Vsystem.

 

Publications:

 

(1)   Janaka Deepakumara, Howard M Heys, and R Venkatesan, "Hardware and Software performance comparison of Message Authentication Code (MAC) Algorithms for Internet Security Protocol (IPSEC)" Proceedings, Newfoundland Electrical and Computer Engineering Conference (NECEC) 2003, November, 2003.

(2)   Janaka Deepakumara, Howard M. Heys and R Venkatesan "Performance of FPGA implementation of Hashed Message Authentication Code-Secure Hash Algorithm (HMAC-SHA)", Newfoundland Electrical and Computer Engineering Conference, (NECEC) 2001 November 13, 2001.

(3)   J. Deepakumara, H.M. Heys, and R. Venkatesan, "FPGA Implementation of MD5 Hash Algorithm", Proceedings of IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2001), Toronto, Ontario, May 2001.
[Abstract]  (Copyright 2001 IEEE)

 

(4)   J. Deepakumara, H.M. Heys, and R. Venkatesan, "Hardware Implementation of MD5 Hash Algorithm", in proceedings of Newfoundland Electrical and Computer Engineering Conference, Nov. 15, 2000.

(5)    Ji Xie, Janaka Deepakumara, Kannan Karthik and Madusudanan. T, Paul Gillard and R. Venkatesan, “Pipelined MUNDLX Processor” In Proceedings, Newfoundland Electrical and Computer Engineering Conference, NECEC 1999,10th November 1999.


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[Faculty of Engineering]   [Center for  Digital Hardware Applications Research (CDHAR)]

Other Links related to my research:

Advanced Encryption Standard (AES):

Federal Information Processing Standards Publications (FIPS)

Request For Comments (RFC) - Index

Canadian Microelectronics Corporation (CMC)

Xilinx Support