Lecture time: | (Tue, Thur) 14:30-15:45 |

Lecture room: | EN-1001 |

Office hour: | (Tue, Thur) 15:45-16:45 |

Lab(EN-3065): | Thursday 9:00-12:00 |

[2012.02.27]: Sample Midterm Exam:

[2012.03.31]: Sample answers for assignments 4 is available through the following links:

[2012.03.31]: The format and weight of the final exam (tentative) is:

True/False .......................... 10

Multiple choice ...................... 5

Short Answer/Calculation/Analysis ... 45

Design .............................. 50

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Total............................... 110

[2012.03.31]: Sample final exam questions:

[2012.2.09]: Sample testbench code for file access can be found at click here.

[2012.1.5]: Welcome Back! My office is in EN-4012, and the phone number is 864 8972.

- C. Roth,
*Digital Systems Design Using VHDL (2nd Edition)*, CL-Engineering Publisher, March 2007 (ISBN-10: 0534384625, ISBN-13: 978-0534384623)

1. | Concepts of Digital Logic and Principles of Digital Circuits Design |

2. | Advanced Minimization Techniques |

3. | Design of Logic Circuits with Programmable Logic Devices (PLDs, FPGAs) |

4. | Introduction to ASICs and ASIC Design Methodology |

5. | Analysis, Modeling and Partitioning for Logic Synthesis and VHDL Coding |

6. | Constraining Designs, Synthesizing, Simulation and Optimization |

7. | Design for Testability, Built-In Self-Test, and Fault Tolerance |

8. | Digital System Reliability |

9. | Noise and Transmission Line Effects |

Problem Sets(4) | 0% (Due: Jan. 24, Feb. 16, Mar. 15, Mar. 29) |

Labs | 30% |

Mid-term | 20% (Mar. 1, 2012 (Tentative)) |

Fianl Exam | 50% |

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*Webpage created by Cheng Li
Last modified:
Sat 2012.01.02 at 18:12 NDT
by Cheng Li
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