| Lecture time: | (Tuesday, Thursday) 9:00-10:15 |
| Lecture room: | EN-1051 |
| Office hour: | Monday 14:00-16:30, or by individual appointment |
| Lab(EN-3076): | Friday 14:00-17:00 |
[2006.5.1]: My office is in EN-4012, and the phone number is 737 8972.
| 1. | Introduction to CMOS Processing Technology and CMOS Digital Circuit and Logic Design |
| 2. | Introduction to ASICs and ASIC Design Methodology |
| 3. | Basic Concepts about Synopsys and ASIC Technology Library |
| 4. | Partitioning for Logic Synthesis and VHDL Coding |
| 5. | Constraining Designs, Synthesizing, Simulation and Optimization |
| 6. | Design for Testability |
| 7. | Layout & Post-layout Optimization and SDF Generation |
| 8. | Static Timing Analysis |
| 9. | Getting Toward Production* |
| Assignments | 10% |
| Labs | 20% |
| Mid-term | 20% |
| Fianl Exam | 50% |
Webpage created by Cheng Li
Last modified:
Sat 2006.05.01 at 18:12 NDT
by Cheng Li