| Lecture time: | Friday 14:00 - 17:00 |
| Lecture room: | EN-1001 |
| Office hour: | Monday, Wednesday 14:00 - 15:00, or by individual appointment |
| Lab (Room: EN-4008/02): | Thursday 14:00 - 17:00 |
[2016.01.05]: Welcome to ENGI-9865, Advanced Digital Systems! My office is in EN-4012, and the phone number is 864 8972.
[2016.01.29]: Sample testbench code for file access can be found at click here.
| 1. | Concepts of Digital Logic and Principles of Digital Circuits Design |
| 2. | Advanced Minimization Techniques |
| 3. | Design of Logic Circuits with Programmable Logic Devices (PLDs, FPGAs) |
| 4. | Introduction to ASICs and ASIC Design Methodology |
| 5. | Analysis, Modeling and Partitioning for Logic Synthesis and VHDL Coding |
| 6. | Constraining Designs, Synthesizing, Simulation and Optimization |
| 7. | Design for Testability, Built-In Self-Test, and Fault Tolerance |
| 8. | Digital System Reliability |
| 9. | Noise and Transmission Line Effects |
| 10. | Dealing with Asynchronous Boundaries |
| Mini-Labs(3) | 6% |
| Design Project | 29% |
| Problem Sets(4) | 0% |
| Mid-term | 20% |
| Fianl Exam | 45% |
| Problem Sets: | Due: Jan 29, Feb. 12, Mar. 4, Mar. 18 |
| Project Proposal: | Jan.22, 2016 |
| Mid-Term: | Feb. 19, 2016 (Tentative) |
| Project Meeting: | Week of Feb. 29 - Mar. 4, 2016 (Schedule will be posted later.) |
| Project Presentation: | Week of Mar. 14-25, 2016 (Schedule will be posted later.) |
| Project Demo: | Week of Mar. 14-25, 2016 (Schedule will be posted later.) |
| Project Report: | Apr. 8, 2016 |
Webpage created by Cheng Li
Last modified:
Sat 2016.01.06 at 18:12 NDT
by Cheng Li