| Lecture time: | Tuesday, Thursday 12:30 - 13:45 |
| Lecture room: | EN-4008 |
| Office hour: | Monday 14:00 - 16:00, or by individual appointment |
| Lab (Room: TBD): | Monday 14:00 - 17:00 |
[2012.2.09]: Sample testbench code for file access can be found at click here.
[2012.1.10]: Welcome to ENGI-9865, Advanced Digital Systems! My office is in EN-4012, and the phone number is 864 8972.
| 1. | Concepts of Digital Logic and Principles of Digital Circuits Design |
| 2. | Advanced Minimization Techniques |
| 3. | Design of Logic Circuits with Programmable Logic Devices (PLDs, FPGAs) |
| 4. | Introduction to ASICs and ASIC Design Methodology |
| 5. | Analysis, Modeling and Partitioning for Logic Synthesis and VHDL Coding |
| 6. | Constraining Designs, Synthesizing, Simulation and Optimization |
| 7. | Design for Testability, Built-In Self-Test, and Fault Tolerance |
| 8. | Digital System Reliability |
| 9. | Noise and Transmission Line Effects |
| 10. | Dealing with Asynchronous Boundaries |
| Mini-Labs(3) | 6% |
| Design Project | 29% |
| Problem Sets(4) | 0% |
| Mid-term | 20% |
| Fianl Exam | 45% |
| Problem Sets: | Due: Jan 25, Feb. 8, Mar. 15, Mar. 31 |
| Project Proposal: | Jan.28, 2011 |
| Mid-Term: | Mar. 01, 2011 (Tentative) |
| Project Meeting: | Week of Mar. 14-18, 2011 (Schedule will be posted later.) |
| Project Presentation: | Week of Mar. 21-25, 2011 (Schedule will be posted later.) |
| Project Demo: | Week of Mar. 28-Apr. 1, 2011(Schedule will be posted later.) |
| Project Report: | Apr. 8, 2011 |
Webpage created by Cheng Li
Last modified:
Sat 2011.01.03 at 18:12 NDT
by Cheng Li