Instructor: Dr. Lihong Zhang, Faculty of Engineering and Applied Science, Memorial University of Newfoundland, Email: lzhang@mun.ca
Lectures: Three lectures per week. Tuesdays and Thursdays 12:00-12:50, Fridays 13:00-13:50, all in EN-1004
Office Hours: Mondays and Tuesdays 14:00-15:00
Assignment Due Dates: May 21 (A1), May 28 (A2), June 6 (A4), June 14 (A5)
Labs: 9 lab sessions plus final report. The software used for the labs includes CAD tools from Cadence, Synopsys, Mentor Graphics (Siemens EDA now), etc.
Midterm Test: June 25
Project Report: Aug. 2
Evaluation Scheme:
For undergraduate students, the following marking scheme is used:
Assignments: 10 %
Labs: 15 %
Midterm exam: 20 % (Tentatively June 25, Tuesday 12:00-12:50)
Final exam: 55 %
For graduate students, the following marking scheme is used:
Assignments: 10 %
Labs: 15 %
Midterm exam: 20 % (Tentatively June 25, Tuesday 12:00-12:50)
Final exam: 40 %
Project: 15%
Website: The formal D2L based course website is available at http://online.mun.ca
Prerequisite and Contents:
As a prerequisite, students are expected to have basic knowledge on VHDL,
digital logic, digital system design, and microprocessors.
The topics will include, but not be limited to:
1. Introduction to CMOS processing technology and CMOS digital circuit and logic
design
2. Introduction to ASICs and ASIC design methodology
3. Basic concepts about Synopsys and ASIC technology library
4. Partitioning for logic synthesis and VHDL coding
5. Constraining designs, synthesizing, simulation and optimization
6. Design for testability
7. Layout & post-layout optimization and SDF generation
8. Static timing analysis
9. Analog and mixed-signal integrated circuits
Textbook:
There is no official textbook for this course. Most of the
material for lectures and labs is covered by the following books:
1. Michael J. S. Smith, Application-Specific Integrated Circuits,
Pearson, 2011.
2. Himanshu Bhatnagar, Advanced ASIC Chip Synthesis: Using Synopsys Design
Compiler, Physical Compiler and Primetime, Kluwer Academic Publishers,
Boston, 2002.
3. Jan Rabaey, Anantha Chandrakasan, and Borivoje Nikolic, Digital Integrated
Circuits, Prentice Hall, New York,
2014.
4. Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill,
New York, 2016.
5. Neil Weste and David Harris, CMOS VLSI Design, A Circuits and Systems
Perspective, Addison Wesley, Boston, 2010.
6. R. Jacob Baker, CMOS: Circuit Design, Layout, and
Simulation, Wiley-IEEE Press, 4th Edition, 2019.
Last Modified: Sun., May 05, 2024 (at 13:00) by Lihong Zhang