| | Instructor: Cheng Li, EN-4012, 864-8972, licheng@mun.ca
| 1. Lab Requirement |
Notes in .pdf |
Jan. 2 |
| 2. Tutorial for ModelSim |
Notes in .pdf |
Jan. 2 |
| 3. Chapter 1: Introduction to Digital Logic and Digital System |
Notes in .pdf |
Jan. 6 - Jan. 18 |
| 4. Chapter 2: Basic Features of VHDL |
Notes in .pdf |
Jan. 20 - Feb. 17 |
| 5. Chapter 3: Digital System Design and Design Methodology and Minimization Techniques |
Notes in .pdf |
Feb. 24 - Mar. 1 |
| 6. Chapter 4: Programmable Logic Devices |
Notes in .pdf |
Mar. 3 - Mar. 8 |
| 7. Chapter 5: Digital System Testing |
Notes in .pdf |
Mar. 10 - Mar. 22 |
| 8. Chapter 6: Reliability, Transmission Line Effects, Noise in Digital Systems |
Notes in .pdf |
Mar. 24 - Mar. 30 |
| 9. Chapter 7: Deal with Asynchronous Boundaries |
Notes in .pdf |
Mar. 30 - Apr. 5 |
| 10. Chapter 8: Desgin Example: MIPS R2000 Processor |
Notes in .pdf |
Mar. 30 - Apr. 5 |
Last updated on Jan 2, 2012. |